The optimal number and location of grounded vias to reduce crosstalk

Progress in Electromagnetics Research

Volumn 95, Issue , 2009, Pages 241-266

  Huang, W T ^a   Lu, C H ^b   Lin, D B ^b  

^a MINGHSIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

^b NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; FREQUENCY DOMAIN ANALYSIS; MICROSTRIP DEVICES; PRINTED CIRCUIT BOARDS;

ELECTRONIC PRODUCT; FAR END CROSSTALK; FREQUENCY DOMAINS; NEAR END CROSS TALKS; OPTIMAL PERFORMANCE; PRINTED CIRCUIT BOARD LAYOUT; SIGNAL INTEGRITY; TIME-DOMAIN SIMULATIONS;

TIME DOMAIN ANALYSIS;

EID: 70349540349     PISSN: 10704698     EISSN: 15598985     Source Type: Journal    
DOI: 10.2528/PIER09071709     Document Type: Article

References (17)

1. Sharawi, M. S., "Practical issues in high speed PCB design," IEEE Potentials, Vol. 23, No. 2, 24-27, Apr./May 2004.
2. Bogatin, E., Signal Integrity-simplified, Prentice Hall, 2003.
3. Montrose, M.I., EMC and the Printed Circuit Board: Design, Theory, and Layout Made Simple, IEEE Press, 1998.
4. Rossi, D., P. Angelini, C. Metra, G. Campardo, and G. Vanalli, "Risks for signal integrity in system in package and possible remedies," 13th IEEE European Test, 165-170, May 2008.
5. Novak, I., B. Eged, and L. Hatvani, "Measurement by vector- network analyzer and simulation of crosstalk reduction on printed board with additional center traces," IEEE Institute of Technology Conference, 269-274, Irvine, CA, 1993.
6. Novak, I., B. Eged, and L. Hatvani, "Measurement and simulation of crosstalk reduction by discrete discontinuities along coupled PCB traces," IEEE Transactions on Instrumentation and Measurement, Vol. 43, No. 2, 170-175, Apr. 1994.
7. Ladd, D. N. and G. Costache, "SPICE simulation used to characterize the cross-talk reduction effect of additional tracks grounded with vias on printed circuit boards," IEEE Transaction on Circuits and Systems II, Vol. 39, 342-347, Jun. 1992.
8. Cheng, Y. S., W. D. Guo, G. H. Shine, H. H. Cheng, C. C. Wang, and R. B. Wu, "Fewest vias design for microstrip guard trace by using overlying dielectric," IEEE Electrical Performance of Electronic Packaging, 321-324, Oct. 2008.
9. Suntives, A., A. Khajooeizadeh, and R. Abhari, "Using via fences for crosstalk reduction in PCB circuits," IEEE International Symposium on Electromagnetic Compatibility, Vol. 1, 34-37, Aug. 2006.
10. Lee, K., H. B. Lee, H. K. Jung, J. Y. Sim, and H. J. Park, "A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines," IEEE Transactions on Advanced Packaging, Vol. 31, No. 4, 809-817, Nov. 2008.
11. Hall, S. H., G. W. Hall, and J. A. McCall, High-speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, John-Wiley & Sons, 2000.
12. Young, B., Digital Signal Integrity: Modeling and Simulations with Interconnects and Packages, Prentice-Hall, 2001.
13. Muthana, P. and H. Kroger, "Behavior of short pulses on tightly coupled microstrip lines and reduction of crosstalk by using overlying dielectric," IEEE Transactions on Advanced Packaging, Vol. 30, No. 3, 511-520, Aug. 2007.
14. Cheng, D. K., Field and Wave Electromagnetics, 2nd edition, Addison-Wesley, 1989.
15. Sobol, H., "Applications of integrated circuit technology to microwave frequencies," Proceedings of the IEEE, 1200-1211, Aug. 1971.
16. Advance Allegro PCB SI Techniques V15.2, Cadence, 2005.
17. Mbairi, F. D., W. P. Siebert, and H. Hesselbom, "On the problem of using guard traces for high frequency differential lines crosstalk reduction," IEEE Transactions on Components and Packaging Technologies, Vol. 30, No. 1, 67-74, Mar. 2007.