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Volumn 5506 LNCS, Issue PART 1, 2009, Pages 1129-1136

FPGA implementation of an evolving spiking neural network

Author keywords

[No Author keywords available]

Indexed keywords

FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS; FPGA CHIPS; FPGA IMPLEMENTATIONS; INTEGRATE-AND-FIRE NEURONS; LOGIC ELEMENTS; ONLINE LEARNING; RECOGNITION MODELS; SOFTWARE SIMULATION; SPIKING NEURAL NETWORKS; STAND -ALONE; WHOLE SYSTEMS;

EID: 70349146655     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-02490-0_137     Document Type: Conference Paper
Times cited : (10)

References (10)
  • 2
    • 34248645728 scopus 로고    scopus 로고
    • Feedforward neural network implementation in fpga using layer multiplexing for effective resource utilization
    • Himavathi, S., Anitha, D., Muthuramalingam, A.: Feedforward Neural Network Implementation in FPGA Using Layer Multiplexing for Effective Resource Utilization. IEEE Tran. on Neural Networks 18(3), 880-888 (2007)
    • (2007) IEEE Tran. on Neural Networks , vol.18 , Issue.3 , pp. 880-888
    • Himavathi, S.1    Anitha, D.2    Muthuramalingam, A.3
  • 4
    • 39049108424 scopus 로고    scopus 로고
    • FPGA implementation of a face detector using neural networks
    • IEEE Press, Los Alamitos
    • Lee, Y., Ko, S.-B.: FPGA Implementation of a Face Detector Using Neural Networks. In: IEEE Conference on Electrical and Computer Engineering, pp. 1914-1917. IEEE Press, Los Alamitos (2006)
    • (2006) IEEE Conference on Electrical and Computer Engineering , pp. 1914-1917
    • Lee, Y.1    Ko, S.-B.2
  • 5
    • 33750312933 scopus 로고    scopus 로고
    • On-chip genetic algorithm optimized pulse based RBF neural network for unsupervised clustering problem
    • Jiao, L., Wang, L., Gao, X.-b., Liu, J., Wu, F. (eds.) ICNC 2006. Springer, Heidelberg
    • Low, K.-S., Krishnan, V., Zhuang, H., Yau, W.-Y.: On-chip genetic algorithm optimized pulse based RBF neural network for unsupervised clustering problem. In: Jiao, L., Wang, L., Gao, X.-b., Liu, J., Wu, F. (eds.) ICNC 2006. LNCS, vol.4222, pp. 851-860. Springer, Heidelberg (2006)
    • (2006) LNCS , vol.4222 , pp. 851-860
    • Low, K.-S.1    Krishnan, V.2    Zhuang, H.3    Yau, W.-Y.4
  • 6
    • 84942426443 scopus 로고    scopus 로고
    • Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot
    • IEEE Press, Los Alamitos
    • Roggen, D., Hofmann, S., Thoma, Y., Floreano, D.: Hardware spiking neural network with run-time reconfigurable connectivity in an autonomous robot. In: NASA/DoD Conference on Evolvable Hardware, pp. 189-198. IEEE Press, Los Alamitos (2003)
    • (2003) NASA/DoD Conference on Evolvable Hardware , pp. 189-198
    • Roggen, D.1    Hofmann, S.2    Thoma, Y.3    Floreano, D.4
  • 8
    • 33749842514 scopus 로고    scopus 로고
    • On-Line learning with structural adaptation in a network of spiking neurons for visual pattern recognition
    • Kollias, S.D., Stafylopatis, A., Duch, W., Oja, E. (eds.) ICANN 2006. Springer, Heidelberg
    • Wysoski, S.G., Benuskova, L., Kasabov, N.: On-Line Learning with Structural Adaptation in a Network of Spiking Neurons for Visual Pattern Recognition. In: Kollias, S.D., Stafylopatis, A., Duch, W., Oja, E. (eds.) ICANN 2006. LNCS, vol.4131, pp. 61-70. Springer, Heidelberg (2006)
    • (2006) LNCS , vol.4131 , pp. 61-70
    • Wysoski, S.G.1    Benuskova, L.2    Kasabov, N.3
  • 10
    • 70349114755 scopus 로고    scopus 로고
    • Comparison between software and FPGA implementation of ESNN in terms of processing speed
    • Electronics New Zealand Incorporated
    • Soltic, S., Zuppicich, A.: Comparison between software and FPGA implementation of ESNN in terms of processing speed. In: 15th Electronics New Zealand Conference, pp. 56-61. Electronics New Zealand Incorporated (2008)
    • (2008) 15th Electronics New Zealand Conference , pp. 56-61
    • Soltic, S.1    Zuppicich, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.