FPGA implementation of programmable pulse mode neural network with on chip learning

Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

Volumn , Issue , 2006, Pages 441-444

  Damak, Alima ^a   Krid, Mohamed ^a   Sellami Masmoudi, Dorra ^a   Derbel, Nabil ^a  

^a UNIVERSITY OF SFAX   (Tunisia)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION FUNCTIONS; FPGA IMPLEMENTATIONS; HARDWARE COST; LEARNING CAPABILITIES; MULTIPLIERLESS; MULTIPLIERLESS ARCHITECTURE; ON-CHIP LEARNING; PROPOSED ARCHITECTURES; PULSE MODES; PULSE MULTIPLIER; SIGNATURE RECOGNITION; XILINX FPGA;

DESIGN; INTEGRATED CONTROL; MULTILAYER NEURAL NETWORKS; NANOSTRUCTURED MATERIALS;

NETWORK ARCHITECTURE;

EID: 78650389151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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