VLSI implementation of an edge-oriented image scaling processor

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 9, 2009, Pages 1275-1284

  Chen, Pei Yin ^a   Lien, Chih Yuan ^a   Lu, Chi Pin ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Image scaling; Interpolation; Pipeline architecture; VLSI

Indexed keywords

GATE COUNT; IMAGE EDGE FEATURES; IMAGE PROCESSING APPLICATIONS; IMAGE SCALING; LOW COSTS; LOW-COMPLEXITY; M-TECHNOLOGIES; PIPELINE ARCHITECTURE; PROCESSING RATES; QUANTITATIVE EVALUATION; VISUAL QUALITIES; VLSI; VLSI ARCHITECTURES; VLSI IMPLEMENTATION;

COMPUTER ARCHITECTURE; IMAGE QUALITY; INTERPOLATION; PIPELINES; PIXELS;

ARCHITECTURAL DESIGN;

EID: 69649102890     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2003003     Document Type: Article

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