Real-time FPGA-based architecture for bicubic interpolation: An application for digital image scaling

Proceedings - ReConFig 2005: 2005 International Conference on Reconfigurable Computing and FPGAs

Volumn 2005, Issue , 2005, Pages

  Nuño Maganda, Marco Aurelio ^a   Arias Estrada, Miguel O ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE ANALYSIS; INTERPOLATION; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS;

FPGA-BASED ARCHITECTURE; HARDWARE ARCHITECTURE FOR BICUBIC INTERPOLATION (HABI); IMAGE SCALING;

COMPUTER ARCHITECTURE;

EID: 33846997166     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RECONFIG.2005.34     Document Type: Conference Paper

References (8)

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2. Cesar Torres Huitzil, Miguel O. Arias Estrada.: Configurable Hardware Architecture for Real-Time Window-based Image Processing,. Lecture Notes in Computer Science, Vol 2778, Springer-Verlag, 2003, pp 1008-1011, ISBN 3-540-40822-3.
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