Low-Power 32-bit Dual-MAC 120 μw/MHz 1.0 v icyflex1 DSP/MCU core

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 7, 2009, Pages 2055-2064

  Arm, Claude ^a   Gyger, Stève ^a   Masgonty, Jean Marc ^a   Morgan, Marc ^a   Nagel, Jean Luc ^a   Piguet, Christian ^a   Rampogna, Flavio ^b   Volet, Patrick ^a  

^a CSEM   (Switzerland)

^b RiskMetrics Group   (Switzerland)

Author keywords

Customizable; Digital signal processor (DSP); Icyflex; Microcontroller; Processor architecture; RISC; Run time reconfigurable; Ultra low power

Indexed keywords

CUSTOMIZABLE; ICYFLEX; PROCESSOR ARCHITECTURE; RISC; RUN-TIME RECONFIGURABLE; ULTRA LOW POWER;

CONTROLLERS; MICROCONTROLLERS; REDUCED INSTRUCTION SET COMPUTING; SIGNAL PROCESSING; SOFTWARE ARCHITECTURE; SPEED CONTROL;

DIGITAL SIGNAL PROCESSORS;

EID: 67651171493     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2021924     Document Type: Article

References (10)

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3. C. Arm, J.-M. Masgonty, and C. Piguet, "Double-latch clocking scheme for low-power I.P. cores," presented at the PATMOS 2000 Conf., Goettingen, Germany, Sep. 13-15, 2000.
4. J.-M. Masgonty, S. Cserveny, C. Arm, P.-D. Pfister, and C. Piguet, "Low-power low-voltage standard library cells with a limited number of cells," presented at the PATMOS 2001 Conf., Yverdon, Switzerland, Sep. 26-28, 2001.
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7. C. Arm, S. Gyger, J.-M. Masgonty, M. Morgan, J.-L. Nagel, C. Piguet, F. Rampogna, and P. Volet, "Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU Core," presented at the ESSCIRC 2008, Edinburgh, Scotland, U.K., Sep. 2008.
8. C. Piguet, "Design methodologies for heterogeneous systems and case studies of MPSoC chips," presented at the MPSoC 2008, Invited Talk, Château St. Gerlach, Valkenburg a.d. Geul, The Netherlands, Jun. 23-27, 2008.
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