A fast minimum layout perturbation algorithm for electromigration reliability enhancement

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 56-63

  Chen, Zhan ^a   Heng, Fook Luen ^b  

^a INTEL CORPORATION   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; DEFECTS; ELECTROMIGRATION; ELECTRON EMISSION; FAILURE (MECHANICAL); FAULT TOLERANCE; GRAPHIC METHODS; VLSI CIRCUITS;

CIRCUIT WIRES; DEEP SUB-MICRON; ELECTROMIGRATION RELIABILITY; ERROR REMOVAL; HIGH CURRENT DENSITIES; MAJOR FAILURES; PERTURBATION CRITERIA; PERTURBATION PROBLEMS;

WIRE;

EID: 67650563034     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732151     Document Type: Conference Paper

References (12)

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2. A. Dasgupta and R. Karri, "Electromigration Reliability Enhancement via Bus Activity Dis-Tribution", Proc. of DAC, 1996.
3. J.E. Hall, D.E. Hocevar, P. Yang, and M.J. McGraw, \SPIDER-A CAD System for Modeling VLSI Metalization Patterns, " IEEE Trans. on Computer-Aided Design, Vol. 6, No. 6, November 1987.
4. F.L. Heng, Z. Chen and G. Tellez, A VLSI Artwork Legalization Technique Based on a New Criteria of Minimum Layout Perturbation, " ACM/IEEE Intl. Symp. on Physical Design, pp. 116-121, 1997.
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6. IBM Optimization Subroutine Library, Guide and Reference, Release 2. SC23-0519-03
7. P.C. Li and T.K. Young, \Electromigration: The Time Bomb in Deep-submicron ICs, " IEEE Spectrum, pp. 75-78, Sept. 1996.
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9. F. Miller Maley, \An Observation Concerning Constraint-Based Compaction, " Information Processing Letters 25, pp. 119-122, May 1987.
10. K. Roy and S. Prasad, "Logic Synthesis for Reliability-An Early Start to Controlling Electro-migration and Hot Carrier Effects, " Proc. European DAC, pp. 136-141, 1994.
11. R.H. Tu, E. Rosenbaum, W.Y. Chan, C.C. Li, E. Minami, K. Quader, P.K. Ko and C. Hu, \Berkeley Reliability Tools-BERT, "IEEE Transactions on CAD, Vol. 12, pp. 1524-1534, Oct. 1993.
12. P. Yang et. al., \Design for Reliability: The Major Challenge for VLSI, " Proc. of IEEE, Vol. 81, No. 5, pp. 730-744, May 1993.