A methodology for implementation of the execution phase of artificial neural networks in digital hardware devices

Proceedings - Electronics, Robotics and Automotive Mechanics Conference, CERMA 2008

Volumn , Issue , 2008, Pages 422-427

  Peñaloza, Ulises Castro ^a   Ibarra Esquer, Jorge E ^a   Flores Rios, Brenda L ^a  

^a UNIVERSIDAD AUTÓNOMA DE BAJA CALIFORNIA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL NEURAL NETWORK; DESCRIPTOR; DIGITAL HARDWARE; EXECUTION PHASE; HARDWARE DEVICES; HARDWARE PLATFORM; NETWORK DESIGNER; NETWORK PARAMETERS; SINGLE NEURON; SUM OF PRODUCTS;

AUTOMOBILE ELECTRONIC EQUIPMENT; BACKPROPAGATION; DIGITAL DEVICES; HARDWARE; INTERCONNECTION NETWORKS; NETWORK LAYERS;

NEURAL NETWORKS;

EID: 67650093355     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CERMA.2008.54     Document Type: Conference Paper

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