A fast GDDR5 read CRC calculation circuit with read DBI operation

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 249-252

  Yoon, Sang Sic ^a   Kim, Bo Kyeom ^a   Kim, Yong Ki ^a   Chung, Byong Tae ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATION TIME; CMOS PROCESS TECHNOLOGY; CYCLIC REDUNDANCY CHECK; DATA BUS; ERROR DETECTION CODE; HIGH-SPEED OPERATION;

ELECTRIC FIELD MEASUREMENT; ELECTRIC FIELDS;

ERROR DETECTION;

EID: 67649958449     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708775     Document Type: Conference Paper

References (5)

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3. G. Albertengo and R. Sisto, "Parallel CRC generation," IEEE Micro Mag., vol. 13, no. 5, pp. 63-71, Oct. 1990.
4. Pei, T.-B.; Zukowski, C, "High-speed parallel CRC circuits in VLSI," IEEE Transactions on Communications, vol. 40, no. 4, pp. 653-657, April. 1992.
5. Kun-Jin Lin; Cheng-Wen Wu, "A low-cost realization of multiple-input exclusive-OR gates," ASIC Conference and Exhibit, Proceedings of the Eighth Annual IEEE International, pp. 307-310, Sept. 1995.