10 Gb/s CMOS limiting amplifier for optical links

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 285-287

  Tao, Rui ^a   Berroth, Manfred ^a  

^a UNIVERSITY OF STUTTGART   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

10 GB/ S; CMOS PROCESSS; DYNAMIC RANGE; LIMITING AMPLIFIERS; PARALLEL FEEDBACK; SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS;

ELECTRIC NETWORK TOPOLOGY;

EID: 67649873448     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257128     Document Type: Conference Paper

References (4)

1. Kazuo Hagimoto, Member, IEEE, Yuuzou Miyagawa, Yutaka Miyamoto, Masonobu Ohhata, Member, IEEE, Tatsuhito Suzuki, and Hiroyuki Kikuchi, Member, IEEE "Over 10 Gb/s Regenerators using Monolithic ICs for Lightwave Communication Systems" IEEE Journal on Selected Areas in Communications, Vol. 9, No 5, pp. 673-682, June 1991.
2. L. Ingmar Andersson, Member, IEEE et al "Silicon Bipolar Chipset for SONET/SDH lOGb/s Fiber-optic Communication Links" IEEE JSSC, Vol. 30, No. 3, pp210-217, March 1995.
3. M. Lang, Zhi-Gong Wang, Zhihao Lao, N. Schlechtweg, Sedler, W. Bronner, G. Kaufel, K. Kohler, A. Hulsmann and B. Raynor "20-40 Gb/s 0. 2um GaAs HEMT Chip Set for Optical Data Receiver" IEEE JSSC Vol. 32 No. 9 September 1997 ppl384-1393.
4. E. M Cherry, M. Sc, Ph. d, and D. E. Hopper, M. E. Gradulates: "The Design of Wide-Band Transistor Feedback Amplifiers", IEE Proc. VOL. 110, No. 2, Feb, pp375-389, 1963.