Fast chirplet transform with FPGA-based implementation

IEEE Signal Processing Letters

Volumn 15, Issue , 2008, Pages 577-580

  Lu, Yufeng ^a   Oruklu, Erdal ^b   Saniie, Jafar ^b  

^a BRADLEY UNIVERSITY   (United States)

^b Illinois Institute of Technology   (United States)

Author keywords

Detection; Estimation; Fast chirplet transform; Field programmable gate arrays; Hardware software co design

Indexed keywords

ALGORITHM IMPLEMENTATION; CHIRPLET; CHIRPLET TRANSFORMS; CHIRPLETS; COMPUTATIONALLY EFFICIENT; DETECTION; DEVELOPMENT PLATFORM; EMBEDDED IMPLEMENTATION; FAST CHIRPLET TRANSFORM; FCT ALGORITHM; FPGA-BASED IMPLEMENTATION; HARDWARE/SOFTWARE CO-DESIGN; LINEAR EXPANSIONS; NARROW BANDS; OBJECT CLASSIFICATION; PHYSICAL INTERPRETATION; REAL-TIME APPLICATION; SYSTEM CONSTRAINTS; SYSTEM ON CHIPS; TARGET DETECTION;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONVOLUTION; DATA COMPRESSION; ESTIMATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INERTIAL CONFINEMENT FUSION; LOGIC GATES; OBJECT RECOGNITION; PATTERN RECOGNITION; SIGNAL DETECTION; ULTRASONIC APPLICATIONS; UNDERWATER ACOUSTICS; VELOCITY MEASUREMENT;

DECONVOLUTION;

EID: 67649358445     PISSN: 10709908     EISSN: None     Source Type: Journal    
DOI: 10.1109/LSP.2008.2001816     Document Type: Article

References (11)

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