Design considerations for a 10ghz cmos transmit-receive switch

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2104-2107

  Naegle, Kristen M ^a   Gupta, Subhanshu ^a   Allstot, David J ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESS; DC BIAS; DESIGN CONSIDERATIONS; FIGURE OF MERIT; IMPEDANCE MATCHING NETWORK; ISOLATION CHARACTERISTICS; PARALLEL RESONANT; SIMULATION MODEL; T/R SWITCH; TRANSMIT/RECEIVE SWITCHES; TRIPLE WELL;

BANDPASS FILTERS; IMPEDANCE MATCHING (ELECTRIC); LINEARIZATION; SWITCHES;

SWITCHING CIRCUITS;

EID: 67649238239     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465034     Document Type: Conference Paper

References (6)

1. Z. Li and K.K. O, "A 15GHz integrated CMOS switch with 21.5dBm IP1dB and 1.8-dB insertion loss," IEEE Symp. on VLSI Circuits, pp. 366-367, 2004.
2. N. Talwalkar, P. Yue, and S.S. Wong, "Integrated CMOS Transmit-Receive switch using LC-tuned substrate bias for 2.4GHz and 5.2GHz applications," IEEE J. Solid-State Circuits, vol. 39, pp. 863-870, June 2004.
3. H. Takasu, et al., "W-band SPST transistor switches," IEEE Microwave and Guided Wave Letters, vol. 6, pp. 315-316, Sept. 1996.
4. D.M. Pozar, Microwave Engineering, NY: Wiley, 1998, pp. 208-211.
5. T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. USA: Cambridge University Press, 1998, pp. 297-300.
6. Z. Li, H. Yoon, F. Yuang, K.K. O, "5.8-GHz CMOS T/R switches with high and low substrate resistances in a 0.18-/spl mu/m CMOS process", IEEE Microwave and Wireless Components Letters, vol. 13, no. 1, pp. 1-3, Jan. 2003.