A memory access system for merged memory with logic LSIs

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 384-387

  Kim, Youngsik ^a   Han, Tack Don ^a   Kim, Shin Dug ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 67649104459     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824114     Document Type: Conference Paper

References (7)

1. D. Patterson, et al, "Intelligent RAM(IRAM): Chips that remember and compute, " Dig. Tech. Papers IEEE Int'l Solid-State Circuit Conf, pp. 224-225, 1997.
2. K. Murakami, et al, "Parallel processing RAM chip with 256Mbits DRAM and quad processors, " Dig. Tech. Papers IEEE Int'l Solid-State Circuit Conf., pp. 228-229, 1997.
3. Y. Kim, T. D. Han and S. D. Kim, "Impact of the memory interface structure in the memory-processor integrated architecture for computer vision, " accepted for Journal of Systems Architecture, 1999.
4. T. Yamauchi, L. Hammond, K. Olukotun, "A single chip multiprocessor integrated with DRAM, " Workshop on Mixing Logic and DRAM with ISCA97, 1997.
5. T. Yamauchi, L. Hammond, K. Olukotun, "The hierarchical multi-bank DRAM: A high-performance architecture for memory integrated with processors, " 19th Conf. on Advanced Research in VLSI, 1997.
6. A. Saulsbury, F. Pong, A. Nowatzyk, "Missing the memory wall: The case for processor/memory integration, " Int'l Symposium on Comp. Arch., pp. 90-101, 1996
7. K. Inoue, K. Kai, K. Murakami, "Dynamically variable line-size caches exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs, " Technical Reports, PPRAM-TR-33, Kyushu Univ. Feb. 1998.