Memory access overhead reduction for a digital color copier implementation using a vliw digital signal processor

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1465-1468

  Kang, Moonseok ^a   Sung, Wonyong ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK BASED; BLOCK SIZES; CACHE MISS; CACHING METHODS; DATA CACHES; DIGITAL COLOR; MEMORY ACCESS; PARTIAL BLOCKS; SOFTWARE PIPELINING;

DIGITAL SIGNAL PROCESSORS; SIGNAL PROCESSING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

COMPUTER SOFTWARE;

EID: 67649088651     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464875     Document Type: Conference Paper

References (7)

1. S. H. Ju and W. Sung, "Implementation of a Digital Color Copier Using a VLIW SIMD Architecture," Proc. 2004 IEEE International Conference on Acoustics, Speech and Signal Processing,vol. 5, pp. 933-936, May. 2004.
2. Jae-woo Ahn and Wonyong Sung, "Multimedia processor-based implementation of an error-diffusion halftoning algorithm exploiting subword parallelism," IEEE Trans. on Circuits and Systems for Video Technology, vol. 16, no. 2, pp. 129-138, Feb. 2001.
3. Sanjiv Agarwala et. Al., "A 600MHz VLIW DSP," IEEE Journal of Solid-State Circuit, vol. 37, no. 11, pp. 1532-1544, Nov. 2002.
4. TMS320C64x DSP Two-Level Internal Memory Reference Guide, Literature Num. SPRU610, Texas Instruments, Aug. 2002.
5. TMS320C6000 Cache Users Guide, Literature Num. SPRU656A, Texas Instruments, May 2003.
6. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Francisco, CA, third edition, 2002.
7. TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor, Literature Num. SPRS200G, Texas Instruments, July 2002.