Analyzing the worst-case execution time for instruction caches with prefetching

Transactions on Embedded Computing Systems

Volumn 8, Issue 1, 2008, Pages

  Yan, Jun ^a,b   Zhang, Wei ^a,b  

^a SOUTHERN ILLINOIS UNIVERSITY   (United States)

^b Southern Illinois University Carbondale   (United States)

Author keywords

Hard real time; Instruction caches; Instruction prefetching; Worst case execution time analysis

Indexed keywords

AVERAGE-CASE; CACHE SIMULATION; DESIGN CONSIDERATIONS; EVALUATION RESULTS; HARD REAL-TIME; INSTRUCTION CACHES; INSTRUCTION PREFETCHING; PREFETCHING; TIME VARIATIONS; WORST-CASE EXECUTION TIME; WORST-CASE EXECUTION TIME ANALYSIS; WORST-CASE PERFORMANCE;

CACHE MEMORY;

REAL TIME SYSTEMS;

EID: 67549137647     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1457246.1457253     Document Type: Article

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