Architectural optimization for microelectronic packaging

Applied Thermal Engineering

Volumn 29, Issue 11-12, 2009, Pages 2391-2395

  Mathias, Jean Denis ^a   Geffroy, Pierre Marie ^b   Silvain, Jean François ^c  

^a Cemagref   (France)

^b UNIVERSITY OF LIMOGES   (France)

^c UNIVERSITÉ DE BORDEAUX   (France)

Author keywords

Microelectronic device; Optimization; Thermal loading

Indexed keywords

ARCHITECTURE; GEOMETRY; ITERATIVE METHODS; MICROELECTRONICS; NUMERICAL METHODS; OPTIMIZATION; RELIABILITY ANALYSIS; THERMOELECTRIC EQUIPMENT;

DEVICE RELIABILITY; ELECTRONIC DEVICE; METHODICAL APPROACH; MICRO-ELECTRONIC DEVICES; MICROELECTRONIC PACKAGING; NUMERICAL APPROACHES; POWER MICROELECTRONICS; THERMAL LOADINGS;

ELECTRON DEVICES;

EID: 67349118880     PISSN: 13594311     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.applthermaleng.2008.12.037     Document Type: Article

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