Real-time program execution on NAND flash memory for portable media players

Proceedings - Real-Time Systems Symposium

Volumn , Issue , 2008, Pages 244-255

  Kim, Jong Chan ^a   Lee, Duhee ^a   Lee, Chang Gun ^a   Kim, Kanghee ^b   Ha, Eun Yong ^c  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c Anyang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CODE STORAGE; MEDIA PLAYERS; NAND FLASH MEMORY; PORTABLE MEDIA PLAYER; PROGRAM CODE; PROGRAM DEVELOPERS; PROGRAM TARGETING; REAL TIME PROGRAMS; REAL TIME REQUIREMENT;

ANTENNAS; NAND CIRCUITS; NONVOLATILE STORAGE; REAL TIME SYSTEMS; STATIC RANDOM ACCESS STORAGE;

FLASH MEMORY;

EID: 67249130358     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2008.27     Document Type: Conference Paper

References (24)

1. A.-H. Badawy, A. Aggarwal, D. Yeung, and C.-W. Tseng The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems. Journal of Instruction-Level Parallelism, 6, July 2004.
2. A. Ban. Flash File System Optimized for Page-Mode Flash Technologies. US Patent, No. 5,937,425, Aug. 1999.
3. L.-P. Chang and T.-W. Kuo. An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems. In Proc. of IEEE Real-Time and Embedded Technology and Applications Symposium, pages 187-196, Dec. 2002.
4. L.-P. Chang, T.-W. Kuo, and S.-W. Lo. Real-Time Garbage Collection for Flash-Memory Storage Systems of Real- Time Embedded Systems. ACMTransactions on Embedded Computing Systems, 3(4):837-863, Nov. 2004.
5. R. L. Coulson, J. I.Garney, J.N. Matthews, and R. J. Royer. System Boot Time Reduction Method. US Patent, No. 6,920,533 B2, Jul. 2005.
6. P. G. Harrison and N. M. Patel. Performance Modeling of Communication Networks and Computer Architecture. Addison-Wesley, 1993.
7. W. W. Hwu and P. P. Chang. Achieving High Instruction Cache Performance with an Optimizing Compiler. In Proc. of the 16th Annual International Symposium on Computer Architecture, pages 242-251, June 1989.
8. S. Jain and Y.-H. Lee. A Real-Time Flash-Memory File System (RTFFS) for Embedded Applications. International Journal of Computer and Their Applications, 3(3):153-166, Sept. 2006.
9. H. Jo, J.-U. Kang, S.-Y. Park, J.-S. Kim, and J. Lee. FAB: Flash-Aware Buffer Management Policy for Portable Media Players. IEEE Transactions on Consumer Electronics, 52(2):485-493, May 2006. (Pubitemid 44203122)
10. J.-U. Kang, J.-S. Kim, C. Park, H. Park, and J. Lee. A Multi-Channel Architecture for High-Performance NAND Flash-based Storage System. Journal of Systems Architecture, 53(9):644-658, Sep. 2007. (Pubitemid 46754996)
11. J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A Space-Efficient Flash Translation Layer for CompactFlash Systems. IEEE Transactions on Consumer Electronics, 48(2):366-375, May 2002. (Pubitemid 34798899)
12. Y.-J. Kim, S.-J. Lee, K. Zhang, and J. Kim. I/O Performance Optimization Techniques for Hybrid Hard Disk- Based Mobile Consumer Devices. IEEE Transactions on Consumer Electronics, 53(4):1469-1476, Nov. 2007. (Pubitemid 351279143)
13. MPlayer Team. MPlayer V1.0rc2. *http://www.mplayerhq.hu/.
14. C. Park, J. Lim, K. Kwon, J. Lee, and S. L. Min. Compiler- Assisted Demand Paging for Embedded Systems with Flash Memory. In Proc. of the 4th ACMInternational Conference on Embedded Software, pages 114-124, Sept. 2004.
15. C. Park, J. Seo, S. Bae, H. Kim, S. Kim, and B. Kim. A Low-cost Memory Architecture with NAND XIP for Mobile Embedded Systems. In Proc. of the 1st IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and System Synthesis, pages 138-143, Oct. 2003.
16. S.-Y. Park, D. Jung, J.-U. Kang, J.-S. Kim, and J. Lee. CFLRU: A Replacement Algorithm for Flash Memory. In Proc. of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 234-241, Oct. 2006.
17. R. Rakvic, B. Black, and J. P. Shen. Completion Time Multiple Branch Prediction for Enhancing Trace Cache Performance. In Proc. of the 27th annual international symposium on Computer architecture (ISCA 00, pages 47-58, 2000. (Pubitemid 30881522)
18. V. K. Reddy, R. K. Sawyer, and E. F. Gehringer. A Cache- Pinning Strategy for Improving Generational Garbage Collection. In Proc. of the 13th IEEE International Conference on High Performance Computing (HiPC-13), pages 98-110, Dec. 2006.
19. G. Reinman, B. Calder, and T. Austin. Fetch Directed Instruction Prefetching. In Proc. of the 32nd International Symposium on Microarchitecture, pages 16-27, 1999. (Pubitemid 30516588)
20. J. T. Robinson, R. B. Tremaine, and M. E. Wazlowski. Weighted Cache Line Replacement. US Patent Application, No. 10/279,246, Apr. 2004.
21. Samsung Electronics Co. K9F2G08UXA 256M x 8 Bit NAND Flash Memory. *http://www.samsung.com/global/business/semiconductor/, Aug. 2006.
22. K. Skadron, P. S. Ahuja, M. Martonosi, and D. W. Clark. Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. IEEE Transactions on Computers, 48(11):1260-1281, Nov. 1999. (Pubitemid 32212125)
23. H. Tomiyama and H. Yasuura. Code Placement Techniques for Cache Miss Rate Reduction. ACM Transactions on Design Automation of Electronic Systems, 2(4):410-429, Oct. 1997. (Pubitemid 127759532)
24. I. Toshiba America Electronic Components. Cost Savings with NAND Shadowing Reference Design with Motorola MPC8260 and Toshiba CompactFlash, 2002.