Performance evaluation of three-level Z-source inverters under semiconductor-failure conditions

IEEE Transactions on Industry Applications

Volumn 45, Issue 3, 2009, Pages 971-981

  Gao, Feng ^a   Loh, Poh Chiang ^a   Blaabjerg, Frede ^b   Vilathgamuwa, D Mahinda ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b AALBORG UNIVERSITY   (Denmark)

Author keywords

Fault compensation; Three level inverter; Z source inverter

Indexed keywords

COMMON MODE VOLTAGE; COMPENSATION METHOD; EXPERIMENTAL TESTING; FAILURE CONDITIONS; FAULT COMPENSATION; FAULT-TOLERANT; GATING SIGNALS; OUTPUT QUALITY; PERFORMANCE EVALUATION; RIDE-THROUGH; TECHNIQUES USED; THREE-LEVEL; THREE-LEVEL INVERTER; THREE-LEVEL INVERTERS; UNIQUE FEATURES; Z-SOURCE INVERTER;

EID: 66949180475     PISSN: 00939994     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIA.2009.2018979     Document Type: Article

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