Memory accesses management during high level synthesis

Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Volumn , Issue , 2004, Pages 42-47

  Corre, Gwenolé ^a   Senn, Eric ^a   Bomel, Pierre ^a   Julien, Nathalie ^a   Martin, Eric ^a  

^a UNIVERSITÉ DE BRETAGNE SUD   (France)

Author keywords

Behavioral synthesis; Memory aware

Indexed keywords

ALGORITHMS; AUTOMATION; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; CONSTRAINT THEORY; IMAGE PROCESSING; SCHEDULING; STORAGE ALLOCATION (COMPUTER);

BEHAVIORAL SYNTHESIS; CONTROL AND DATA FLOW GRAPHS (CDFG); DATA FLOW GRAPHS (DFG); MEMORY AWARE;

DATA STORAGE EQUIPMENT;

EID: 16244397109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016733     Document Type: Conference Paper

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