Data compression with restricted parsings

Data Compression Conference Proceedings

Volumn , Issue , 2006, Pages 203-212

  Franaszek, Peter A ^a   Lastras Montaño, Luis A ^a   Robinson, John T ^a   Peng, Song ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Cornell University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REQUIREMENT; COMPRESSION PERFORMANCE; COMPRESSION SPEED; DATA SETS; ENERGY REQUIREMENTS; EXPERIMENTAL DATA; HARDWARE IMPLEMENTATIONS; IMPLEMENTATION COMPLEXITY; LOWER ENERGIES; MAIN MEMORY; SMALL DATA;

COMPUTER HARDWARE; DATA COMPRESSION RATIO; HARDWARE;

DATA COMPRESSION;

EID: 65749083106     PISSN: 10680314     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DCC.2006.22     Document Type: Conference Paper

References (16)

1. Burrows, M., Wheeler, D.J. "A Block-sorting Lossless Data Compression Algorithm", Research Report SRC-124, DEC, California, May 1994.
2. Craft, D.J., "Method and Apparatus for Compressing Data", US Patent 5, 652, 878
3. Franaszek, P.A., Heidelberger, P., Poff, D.E., Robinson, J.T., "Algorithms and data structures for compressed-memory machines", IBM Journal of Research and Development, vol. 45, No. 2, pp. 245-258, March 2001.
4. Franaszek, P.A., Robinson, J., Thomas, J., "Parallel compression with cooperative dictionary construction", Proceedings of, pp. 200-209.
5. Gonzalez-Smith, M.E. and J.A. Storer,"Parallel algorithms for data compression", Journal of the ACM, vol. 32, Issue 2, pp. 344-373, April 1985
6. IBM Journal of Research and Development Topical Issue on Data compression in ASIC cores, Vol. 42, No. 6, 1998.
7. Kieffer, J.C., Yang, E., "Grammar-Based Codes: A New Class of Universal Lossless Source Codes", IEEE Transactions on Information Theory, Vol. 46, No. 3, May 2000
8. Langdon, G.G., "An introduction to arithmetic coding", IBM Journal of Research and Development, 28: 135-149, 1984. (Pubitemid 14546563)
9. Ranganathan, N, Henriques, S., "High-Speed VLSI Designs for Lempel-Ziv-Based Data Compression", IEEE Transactions on Circuits and Systems II, Vol. 40, No. 2, February 1993.
10. Storer, J. A., Szymanski T.G. "Data Compression Via Textual Substitution", Journal of the ACM, 29:4, (1982) 928-951. (Pubitemid 13450119)
11. Storer, J.A. and Reif, J.H. "A Parallel Architecture for High Speed Data Compression", Journal of Parallel and Distributed Computing 13, 222-227, 1992.
12. Takeda, K., Aimoto, and Y., Nakamura, N. et al. "A 16-Mb 400-MHz Loadless CMOS Four-Transistor SRAM Macro", IEEE Journal of Solid-State Circuits, 35(11), 2000.
13. Tremaine, R.B., Franaszek, P.A., Robinson, J.T., Schulz, C.O., Smith, T.B., Wazlowski, M. and Bland, P.M., "IBM Memory Expansion Technology (MXT)", IBM Journal of Research and Development, vol. 45, No. 2, pp. 271-285, March 2001.
14. Weste, Neil and Harris, David, "CMOS VLSI Design: A Circuits and Systems Perspective", Addison Wesley Publisher, 2005.
15. Ziv, J. and Lempel, A. "A universal algorithm for sequential data compression", IEEE Trans. Inf. Theory 23, 3 (1977), 337-343.
16. Tseng J. H. and Asanovic, K., "Banked Multiported Register Files for High Frequency Superscalar Microprocessors", Proceedings of International Symposium on Computer Architecture, 2003