16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1631-1640

  Takeda, Koichi ^a,b   Aimoto, Yoshiharu ^a,c   Nakamura, Noritsugu ^a,d   Toyoshima, Hideo ^a   Iwasaki, Takahiro ^a   Noda, Kenji ^a   Matsui, Koujirou ^a   Itoh, Shinya ^a   Masuoka, Sadaaki ^a   Horiuchi, Tadahiko ^a   Nakagawa, Atsushi ^a   Shimogawa, Kenju ^a   Takahashi, Hiroyuki ^a  

^a NEC CORPORATION   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

^c NIHON UNIVERSITY   (Japan)

^d KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; PERFORMANCE; RESPONSE TIME (COMPUTER SYSTEMS); TRANSISTORS;

ALL ADJOINING TWISTED BITLINE SCHEME; CMOS LOGIC PROCESS; END POINT DUAL PULSE DRIVER; SHALLOW TRENCH ISOLATION TECHNOLOGY; WORDLINE VOLTAGE LEVEL COMPENSATION CIRCUIT;

STATIC RANDOM ACCESS STORAGE;

EID: 0034316440     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881209     Document Type: Article

References (4)

1. 2 loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology," in IEDM Dig. Tech. Papers, 1998, pp. 74-75.
2. H. Shimizu, K. Ijitsu, H. Akiyoshi, K. Aoyama, H. Takatsuka, K. Watanabe, R. Nanjo, and Y. Takao, "A 1.4-ns access 700-MHz 288-kb SRAM macro with expandable architecture," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 190-191.
3. H. Hidaka, F. Fujishima, Y. Matsuda, M. Asakura, and T. Yoshihara, "Twisted bitline architechture for multi-megabit DRAMs," IEEE J. Solid-State Circuits, vol. 24, pp. 21-28, Feb. 1989.
4. K. Nakamura, K. Takeda, H. Toyoshima, K. Noda, H. Ohkubo, T. Uchida, T. Shimizu, T. Itani, K. Tokashiki, and K. Kishimoto, "A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O," IEEE J. Solid-State Circuits, vol. 32, pp. 1758-1765, Nov. 1997.