High-efficiency control structure for CMOS flash memory charge pumps

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 121-124

  Boffino, C ^a   Cabrini, A ^a   Khouri, O ^b   Torelli, G ^a  

^a UNIVERSITY OF PAVIA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE PUMP; CHARGE PUMP CIRCUIT; CONTROL SCHEMES; CONTROL STRUCTURE; EFFICIENCY IMPROVEMENT; HIGH EFFICIENCY; PORTABLE APPLICATIONS; POWER CONSUMPTION; POWER EFFICIENCY; POWER MANAGEMENTS; POWER-LOSSES;

ENERGY MANAGEMENT; PUMPS;

FLASH MEMORY;

EID: 65649128448     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464539     Document Type: Conference Paper

References (4)

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2. A. Umezawa, S. Atsumi, M. Kuriyama, H. Banba, K. Imamiya, K. Naruke, S. Yamada, E. Obi, M. Oshikiri, T. Suzuki, S. Tanaka, "A 5V-only operation 0.6-μm flash EEPROM with row decoder scheme in triple-well structure", IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1540-1546, November 1992.
3. O. Khouri, R. Micheloni, I. Motta, G. Torelli, "Word-line read voltage regulator with capacitive boosting for multimegabit multilevel Flash memories", Proceedings European Conference on Circuit Theory and Design (ECCTD'99), Stresa, Aug.-Sept. 1999, pp. 145-148.
4. C.-C. Wang, J.-C. Wu, "Efficiency improvement in charge pump circuits", IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 852-860, June 1997.