A formal approach for debugging arithmetic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 5, 2009, Pages 742-754

  Sarbishei, Omid ^a   Tabandeh, Mahmoud ^a   Alizadeh, Bijan ^a   Fujita, Masahiro ^b  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Arithmetic circuits; Logic debugging; Postsynthesis verification

Indexed keywords

ARITHMETIC CIRCUITS; CONVENTIONAL TECHNIQUES; DEBUGGING ALGORITHMS; DESIGN ISSUES; DESIGN OPTIMIZATIONS; EXTRACTION PHASE; FORMAL APPROACHES; LOGIC DEBUGGING; MAPPING ALGORITHMS; MULTIOPERAND ADDERS; NETLIST; PARTIAL PRODUCTS; POSTSYNTHESIS VERIFICATION; RUN-TIME; SIGNAL MAPPINGS; THREE PHASIS;

ADDERS; ALGORITHMS; CONFORMAL MAPPING; INTEGRATING CIRCUITS; SEQUENTIAL CIRCUITS;

PROGRAM DEBUGGING;

EID: 65349155261     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2013998     Document Type: Article

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