Design of multiplierless lattice QMF: Structure and algorithm development

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 2, 2008, Pages 173-177

  Park, Sang Yoon ^a   Cho, Nam Ik ^b,c  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b Seoul National University   (South Korea)

^c Seoul National University   (South Korea)

Author keywords

Lattice; Multiplierless; Quadrature mirror filter (QMF); Signed power of two (SPT); Trellis based searching (TBS)

Indexed keywords

FREQUENCY RESPONSE; MIRRORS;

ALGORITHM DEVELOPMENT; LATTICE; MULTIPLIER-LESS; MULTIPLIERLESS DESIGN; OPTIMIZATION PROGRAMS; POWER-OF-TWO; SIGNED POWERS OF TWOS; TRELLIS-BASED SEARCHING (TBS);

FREQUENCY MULTIPLYING CIRCUITS;

EID: 64849115854     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.910969     Document Type: Article

References (10)

1. P. P. Vaidyanathan, Multirate Systems and Filter Banks. Englewood Cliffs, NJ: Prentice-Hall, 1993.
2. B. R. Horng, H. Samueli, and A. N. Willson Jr., "The design of two-channel lattice-structure perfect-reconstruction filter banks using powers-of-two coefficients," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 40, no. 7, pp. 497-499, Jul. 1993.
3. Y. J. Yu and Y. C. Lim, "A novel genetic algorithm for the design of a signed power-of-two coefficient quadrature mirror filter lattice filter bank," Circuit Syst. Signal Process, vol. 21, no. 3, pp. 263-276, May 2002.
4. Y. C. Lim and Y. J. Yu, "A width-recursive depth-first tree search approach for the design of discrete coefficient perfect reconstruction lattice filter bank," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 6, pp. 257-266, Jun. 2003.
5. S. Y. Park and N. I. Cho, "Design of signed powers-of-two coefficient perfect reconstruction QMF bank using CORDIC algorithms," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 6, pp. 1254-1265, Jun. 2006.
6. A. Y. Wu and C. S. Wu, "A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 49, no. 10, pp. 1442-1456, Oct. 2002.
7. C. H. Lin and A. Y. Wu, "Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 11, pp. 2385-2396, Nov. 2005.
8. Y. H. Hu, "The quantization effects of the CORDIC algorithm," IEEE Trans. Signal Process., vol. 40, no. 4, pp. 834-844, Apr. 1992.
9. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley-Interscience Publications, 1999.
10. Y. C. Lim, J. H. Lee, C. K. Chen, and R. H. Yang, "A weighted least squares algorithm for quasiequiripple FIR and IIR digital filter design," IEEE Trans. Signal Process., vol. 40, no. 3, pp. 551-558, Mar. 1992.