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Volumn , Issue , 2009, Pages 528-534

Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture

Author keywords

[No Author keywords available]

Indexed keywords

CONSUMER DEVICES; HETEROGENEOUS MULTIPROCESSORS; HIGH DEFINITIONS; LANGUAGE MODELS; LOW-POWER CONSUMPTION; MULTI STANDARDS; OPERATING FREQUENCIES; PIXEL PROCESSING; SPECIFIC PROCESSORS; STREAM PROCESSING; VIDEO CODECS;

EID: 64549163213     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796534     Document Type: Conference Paper
Times cited : (2)

References (4)
  • 1
    • 64549126297 scopus 로고    scopus 로고
    • Performance Evaluation of Variable Length Encoder/Decoder Hardware for Multi-Codec,
    • 107, No. 290, pp, Oct
    • Takafumi Yuasa, Hiroaki Nakata, Kazushi Akie, Fumitaka Izuhara, and Kenichi Iwata, "Performance Evaluation of Variable Length Encoder/Decoder Hardware for Multi-Codec," Technical Report of IEICE, Vol. 107, No. 290, pp. 1-5, Oct. 2007.
    • (2007) Technical Report of IEICE , pp. 1-5
    • Yuasa, T.1    Nakata, H.2    Akie, K.3    Izuhara, F.4    Iwata, K.5
  • 2
    • 51949097887 scopus 로고    scopus 로고
    • A 256mW Full-HD H.264 High-Profile CODEC Featuring Dual Macroblock-Pipeline Architecture in 65nm CMOS
    • Jun
    • Kenichi Iwata, et al., "A 256mW Full-HD H.264 High-Profile CODEC Featuring Dual Macroblock-Pipeline Architecture in 65nm CMOS," 2008 Symposium on VLSI Circuits Digest of Technical Papers, pp. 102-103, Jun. 2008.
    • (2008) 2008 Symposium on VLSI Circuits Digest of Technical Papers , pp. 102-103
    • Iwata, K.1
  • 3
    • 63449121805 scopus 로고    scopus 로고
    • Image Processing Technique Using Pipeline Connection MIAD Architecture
    • Aug
    • Koji Hosogi, Masakzu Ehama, Hiroaki Nakata, Tetsuya Shibayama, Seiji Mochizuki, and Kenichi Iwata, "Image Processing Technique Using Pipeline Connection MIAD Architecture," in Proceeding of SWoPP 2007, ARC-2007-174, pp. 55-60, Aug. 2007.
    • (2007) Proceeding of SWoPP , vol.ARC-2007-174 , pp. 55-60
    • Hosogi, K.1    Ehama, M.2    Nakata, H.3    Shibayama, T.4    Mochizuki, S.5    Iwata, K.6
  • 4
    • 39349114149 scopus 로고    scopus 로고
    • Development of Low-power and Real-time VC-1/H.264/ MPEG-4 Video Processing Hardware
    • Jan
    • Masaru Hase, Kazushi Akie, Masaki Nobori, and Keisuke Matsumoto, "Development of Low-power and Real-time VC-1/H.264/ MPEG-4 Video Processing Hardware," in Proceeding of ASP-DAC 2007, pp. 637-643, Jan. 2007.
    • (2007) Proceeding of ASP-DAC , pp. 637-643
    • Hase, M.1    Akie, K.2    Nobori, M.3    Matsumoto, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.