A 256mW full-HD H.264 high-profile CODEC featuring dual macroblock-pipeline architecture in 65nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 102-103

  Iwata, Kenichi ^a   Mochizuki, Seiji ^a   Shibayama, Tetsuya ^a   Izuhara, Fumitaka ^a   Ueda, Hiroshi ^a   Hosogi, Koji ^b   Nakata, Hiroaki ^b   Ehama, Masakazu ^b   Kengaku, Toru ^a   Nakazawa, Takuichiro ^a   Watanabe, Hiromi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

PIPELINES; PROGRAM PROCESSORS; VLSI CIRCUITS;

65NM CMOS; MACRO BLOCK; MACROBLOCK PROCESSING; MULTIPLE STANDARDS; OPERATING FREQUENCY; PIPELINE ARCHITECTURE; REAL-TIME ENCODING; STATE OF THE ART;

CMOS INTEGRATED CIRCUITS;

EID: 51949097887     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585968     Document Type: Conference Paper

References (5)

1. H. C. Chang, et al., "A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip," ISSCC Dig. Tech. Papers, pp. 280-281, Feb. 2007.
2. Y. W. Huang, et al., "A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV Applications," ISSCC Dig. Tech. Papers, pp. 128-129, Feb. 2005.
3. C. D. Chien, et al., "A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications," ISSCC Dig. Tech. Papers, pp. 282-283, Feb. 2007.
4. S. Mochizuki, et al., "A Low Power and High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications," Proc. A-SSCC, pp. 176-179, Nov. 2007.
5. K. Hosogi, et al., "Image Processing Technique Using Pipeline Connection MIAD Architecture," SWoPP2007, ARC-2007-174, pp. 55-60, Aug. 2007.