A 6F2 buried wordline DRAM cell for 40nm and beyond

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Schloesser, T ^a   Jakubowski, F ^a   Kluge, J V ^a   Graham, A ^a   Slesazeck, S ^a   Popp, M ^a   Baars, P ^a   Muemmler, K ^a   Moll, P ^a   Wilson, K ^a   Buerke, A ^a   Koehler, D ^a   Radecker, J ^a   Erben, E ^a   Zimmermann, U ^a   Vorrath, T ^a   Fischer, B ^a   Aichmayr, G ^a   Agaiby, R ^a   Pamler, W ^a   Schuster, T ^a   Bergner, W ^a   Mueller, W ^a   more..

^a QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY PERFORMANCE; ARRAY TRANSISTORS; CELL SIZES; DRAM CELLS; DRAM TECHNOLOGIES; HIGH RELIABILITIES; METAL GATES; ON CURRENTS; PARAMETER VARIABILITIES; PARASITIC CAPACITANCES; SI SURFACES; WORDLINE;

ELECTRON DEVICES; METAL FORMING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 64549124259     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796820     Document Type: Conference Paper

References (5)

1. C.Cho et al., "A 6F2 DRAM Technology in 60nm era for Gigabit Densities", VLSI 2005.
2. W.Mueller et al., "Challenges for DRAM Scaling to 40nm", IEDM 2005.
3. T.Tran et al., "A 58nm Trench DRAM Technology", IEDM 2006.
4. K.Takeuchi et al., "Understanding Random Threshold Voltage Fluctuations", IEDM 2007.
5. J.Amon et al., "A Highly Manufacturable Deep Trench Based DRAM Cell with a Planar Array Device in a 70nm Technology". IEDM 2004.