A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 357-360

  Plouchart, Jean Olivier ^a   Kim, Jonghae ^a   Zamdmer, Noah ^a   Sherony, Melanie ^a   Tan, Yue ^a   Yoon, Meeyoung ^a   Talbi, Mohamed ^a   Ray, Asit ^a   Wagner, Lawrence ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT MODE LOGIC; DIFFERENTIAL VOLTAGE; MAXIMUM OSCILLATION FREQUENCY; OFFSET FREQUENCIES; POWER SUPPLY VOLTAGE; RING VCO; SOI CMOS; TUNING RANGES;

VARIABLE FREQUENCY OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 6444224841     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257146     Document Type: Conference Paper

References (5)

1. Y. K. Boegeman, A. R. Kramer, R. R. Martinez, M. Sokolich, "Demonstration of sub-5 ps CML ring oscillator gate delay with reduced parasitic AlInAs/InGaAs HBT", IEEE Electron Device Lett., Vol. 22, No. 7, pp. 309-311, July 2001.
2. T. Enoki, Y. Ishii, K. Osafune, Y. Umeda, H. Yokoyama, "Analysis of interconnections with BCB for high-speed digital applications", IEEE MTT-S International Microwave Symposium Digest, 1999.
3. D. Ahlgren, et al, "A 4. 2-ps ECL Ring-Oscillator in a 255-GHz fmax SiGe Technology", IEEE Electron Device Lett., Vol. 23, No. 23, pp 541-543, Sep. 2002.
4. B. Razavi, J. Savoj, "A 10 Gb/s CMOS clock and data recovery circuit with frequency detection", IEEE International Solid-State Circuits Conference, 2001.
5. N. Zamdmer, A Ray, J-O. Plouchart, "A 0. 13-um SOI CMOS Technology for Low-power Digital and RF Applications", IEEE VLSI Tech, pp. 85-86, 2001.