Characterization of "Multipath interconnects" for microelectronic and nanotechnology circuits

2002 International Conference on Modeling and Simulation of Microsystems - MSM 2002

Volumn , Issue , 2002, Pages 632-635

  Goel, A K ^a   Eady, N R ^a  

^a Michigan Technological University   (United States)

Author keywords

Capacitances; Green's function; Interconnects; Nanoelectronics; VLSI

Indexed keywords

CAPACITANCE; ELECTROMIGRATION; GREEN'S FUNCTION; MICROELECTRONICS; NANOTECHNOLOGY; NETWORKS (CIRCUITS); SILICON; VLSI CIRCUITS;

INTERCONNECTS; MEDIAN TIME TO FAILURE (MTTF); NANOELECTRONICS; SCHEMATIC DIAGRAM;

INTERCONNECTION NETWORKS;

EID: 6344262310     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A. K. Goel, "Nanotechnology Circuit Design: The Interconnect Problem," Proc. IEEE NANO-2001, Maui, Hawaii, pp. 123-127, October 27-30, 2001.
2. Z. Q. Ning and P. M. Dewilde, "SPIDER: Capacitance modeling for VLSI interconnections" IEEE Trans. Computer-Aided Design, Vol. 7, p.1221, 1998.
3. A. K. Goel, High-Speed VLSI Interconnections, Wiley Interscience, 1994.
4. P. Balaban, "Calculation of the Capacitance Coefficients of Planar Conductors on a Dielectric Surface" IEEE Trans. Circuit Theory, Vol. 6, p.725, 1973.
5. nd Ed., Harper Collins College Publishers, 1995.