Comprehensive modeling of MOS transistors in a 0.35um technology for analog and digital applications

2002 International Conference on Modeling and Simulation of Microsystems - MSM 2002

Volumn , Issue , 2002, Pages 604-607

  Keshavarz, Abdol A ^a   Khare, Prasanna ^a   Sampson, Ronald K ^a  

^a STMicroelectronics USA   (United States)

Author keywords

0.35um MOS Transistor; MOS Modeling; Temperature Effects in MOS Transistors

Indexed keywords

MAXIMUM TRANSCONDUCTANCE; OUTPUT RESISTANCE; SATURATION CURRENT;

ANALOG TO DIGITAL CONVERSION; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; THERMAL EFFECTS; THRESHOLD VOLTAGE; TRANSCONDUCTANCE; TRANSISTORS;

MOS DEVICES;

EID: 6344257090     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Lee et al., "Submicrometer silicon MOSFET's fabricated using focused ion-beam lithography", IEEE Trans. Electron Devices, Vol. ED-33, No. 2, Feb. 1986, page 310-311.
2. G. Guegan, et al., "A 0.35um CMOS process for fast random logic", 1991 IEDM Digest, page 105-108.
3. R.M.D.A Velghe, et al., "MOS MODEL 9", Unclassified report NL-UR 003/94, Philips Research Laboratories, Eindhoven, The Netherlands, June 1995.
4. S. Selberherr, Analysis and Simulation of Semiconductor Devices, Springer-Verlog, New York, 1984, Chaper 4.