A 0.35 mu m CMOS process for fast random logic

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1991-January, Issue , 1991, Pages 105-108

  Guegan, G ^a   Lerme, M ^a   Deleonibus, S ^a   Martin, F ^a   Heitzmann, M ^a   Tedesco, S ^a   Guerin, M ^a   Reimbold, G ^a   Leroux, C ^a   Jaffard, C ^a   Belleville, M ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ELECTRON DEVICES; FIELD EFFECT TRANSISTORS; INTERFACES (MATERIALS); RAPID THERMAL PROCESSING;

BIT MULTIPLICATION; CIRCUIT PERFORMANCE; DEVICE OPTIMIZATION; HIGH-PERFORMANCE CMOS; POWER SUPPLY VOLTAGE; RAPID THERMAL NITRIDATION; SHORT-CHANNEL EFFECT; SPEED PERFORMANCE;

RECONFIGURABLE HARDWARE;

EID: 84910894350     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1991.235413     Document Type: Conference Paper

References (0)