Towards a consistent design methodology for run-time reconfigurable systems

IEE Colloquium (Digest)

Volumn , Issue 61, 1999, Pages 21-24

  Vasilko, Milan ^a   Gibson, Darreil ^a   Long, David ^a   Holloway, Steve ^a  

^a BOURNEMOUTH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL/DATA FLOW GRAPH (CDFG); DESIGN ITERATIONS; RECONFIGURABLE SYSTEMS; REGISTER-TRANSFER LEVEL (RTL);

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; FORMAL LOGIC; GRAPHICAL USER INTERFACES; MATHEMATICAL MODELS; PROGRAM PROCESSORS; SERVERS; VLSI CIRCUITS;

SYSTEMS ANALYSIS;

EID: 6344235823     PISSN: 09633308     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Gibson, M. Vasilko, and D. Long. Virtual prototyping for dynamically reconfigurable systems. In Proceedings of VUIF Fall '98, Orlando, Florida, Oct. 26-28 1998.
2. J. D. Hadley and B. L. Hutchings. Design methodologies for partially reconfigured systems. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 78-84. Napa Valley, CA (USA), Apr. 19-21 1995.
3. M. Kaul and R. Vemuri. Optimal temporal partitioning and synthesis for reconfigurable architectures. In Design, Automation and Test in Europe Conference, Paris, France, Feb. 23-26 1998.
4. P. Lysaght. Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic. In W. Luk, P. Y. K. Cheung, and M. Glesner, editors, Field Programmable Logic and Applications (FPL '97 Proceedings), LNCS1304, pages 183-192. Springer-Verlag, 1997.
5. P. Lysaght and J. Stockwood. A simulation tool for dynamically reconfigurable field programmable gate arrays. IEEE Transactions on VLSI Systems, 4(3):381-390, Sept. 1996.
6. N. Shirazi, W. Luk, and P. Y. Cheung. Automating production of run-time reconfigurable designs. In Proceedings of 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'98), Napa, CA (USA), Apr. 14-17 1998.
7. M. Vasilko and D. Ait-Boudaoud. Architectural synthesis techniques for dynamically reconfigurable logic. In R. W. Hartenstein and M. Glesner, editors, Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, (FPL '96 Proceedings), LNCS 1142, pages 290-296. Springer-Verlag, 1996.
8. M. Vasilko and D. Long. RIFLE-62: A flexible environment for prototyping dynamically reconfigurable systems. In Proceeding of IEEE International Workshop on Rapid System Prototyping (RSP'98), Leuven, Belgium, June 3-5 1998.