3D wafer-scale integration for RF and digital applications

ECS Transactions

Volumn 16, Issue 8, 2009, Pages 243-249

  Chang Chien, P ^a   Gutierrez Aitken, A ^a   Sandhu, R ^a   Hennig, K ^a   Scott, D ^a   Zhou, J ^a   Nam, P ^a   Geiger, C ^a   Poust, B ^a   Parlee, M ^a   Thai, K ^a   Phan, W ^a   Oyama, B ^a  

^a NORTHROP GRUMMAN CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL DEVICES; SEMICONDUCTOR DEVICES; SUBSTRATES; WAFER BONDING; WSI CIRCUITS;

COMPOUND SEMICONDUCTORS; DIGITAL APPLICATIONS; FACE-TO-FACE BONDING; HETEROGENEOUS INTEGRATION; INTEGRATION APPROACH; INTEGRATION TECHNOLOGIES; NORTHROP GRUMMAN SPACE TECHNOLOGIES; SEMICONDUCTOR TECHNOLOGY;

SILICON WAFERS;

EID: 63149147409     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2982875     Document Type: Conference Paper

References (4)

1. A Gutierrez-Aitken, "Epitaxial and non-epitaxial Heterogeneous integration technologies at NGST" MRS Spring 2008 Proceeding, San Francisco CA, March 2008, paper number 1068-C02-02
2. P. Chang-Chien, K. Tornquist, M. Nishimoto, C. Geiger, J. Lee, M. Truong, J. Uyeda, L. Lembo, M. Barsky, R. Lai, and A. Oki. "Low-temperature, Hermetic, High Yield, Wafer-Level Packaging Technology" Northrop Grumman Technology Review Journal, Vol. 14, Spring/summer 2006, pp. 77-97
3. J. Yang, Y. Chung, M. Nishimoto, M. Battling, A. Long, P. Chang-Chien, K. Tornquist, M. Siddiqui and R. Lai. "Wafer level integrated antenna front end module for low cost phased array implementation" IEEE MTT-S International Mcirowave Symposium, IMS 2007, Honolulu, Haiwaii, June 2007, paper number Th4F-04
4. R. Sandhu, P. Chang-Chien, M. Parlee, B. Poust, T. Chung, R. Tsai, A. Noori, V. Temsevary, O. Fordham, X. Zeng, K. Tornquist, D. Duan, T. P. Chin, and M. Barsky "Thermal-Mechanical Characterization of Wafer Level Packaging Technologies" 2008 CSManTech, Chicago IL, April 2008, paper number 14.4