메뉴 건너뛰기




Volumn , Issue , 2008, Pages 145-148

Integrated system development for 3-D VLSI

Author keywords

[No Author keywords available]

Indexed keywords

3-D PACKAGING; 3-D VLSIS; ASSEMBLY TECHNOLOGIES; AUTOMATED TEST SYSTEMS; CHAIN LINKS; DEVICE WAFERS; DIE STACKING; ELECTRICAL CONNECTIONS; FLIP-CHIP ASSEMBLIES; FLIP-CHIP BONDERS; FLUID CHANNELS; FOUR-LAYER STRUCTURES; GAAS; HEAT DISSIPATIONS; HIGH YIELDS; HIGH-POWER; INTEGRATED SYSTEMS; KNOWN-GOOD DIES; LEAK-FREE; METALIZATION; MICRO FLUIDS; PRE-SELECTED; RELIABILITY TESTS; SILICON STRUCTURES; TEMPERATURE SENSING; TEST VEHICLES; THERMAL COMPRESSIONS; THERMAL PERFORMANCE; THERMAL TESTS; TWO LAYERS; WAFER STACKING;

EID: 63049092477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VPWJ.2008.4762237     Document Type: Conference Paper
Times cited : (3)

References (5)
  • 5
    • 33745482433 scopus 로고    scopus 로고
    • Copper electroplating to fill blind vias for three-dimensional integration
    • Jul/Aug
    • Spiesshoefer, S. et al, "Copper electroplating to fill blind vias for three-dimensional integration," J. Vac. Sci Technol A 24(4), Jul/Aug 2006, pp. 1277-1282.
    • (2006) J. Vac. Sci Technol A , vol.24 , Issue.4 , pp. 1277-1282
    • Spiesshoefer, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.