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Volumn , Issue , 2008, Pages 145-148
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Integrated system development for 3-D VLSI
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Author keywords
[No Author keywords available]
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Indexed keywords
3-D PACKAGING;
3-D VLSIS;
ASSEMBLY TECHNOLOGIES;
AUTOMATED TEST SYSTEMS;
CHAIN LINKS;
DEVICE WAFERS;
DIE STACKING;
ELECTRICAL CONNECTIONS;
FLIP-CHIP ASSEMBLIES;
FLIP-CHIP BONDERS;
FLUID CHANNELS;
FOUR-LAYER STRUCTURES;
GAAS;
HEAT DISSIPATIONS;
HIGH YIELDS;
HIGH-POWER;
INTEGRATED SYSTEMS;
KNOWN-GOOD DIES;
LEAK-FREE;
METALIZATION;
MICRO FLUIDS;
PRE-SELECTED;
RELIABILITY TESTS;
SILICON STRUCTURES;
TEMPERATURE SENSING;
TEST VEHICLES;
THERMAL COMPRESSIONS;
THERMAL PERFORMANCE;
THERMAL TESTS;
TWO LAYERS;
WAFER STACKING;
BONDING;
COOLANTS;
COPPER;
DAMS;
DIES;
ELECTRIC CONNECTORS;
ELECTRONIC EQUIPMENT MANUFACTURE;
GOLD;
INTEGRATED OPTICS;
LEAKAGE (FLUID);
RESISTORS;
SEMICONDUCTING SILICON COMPOUNDS;
SILICON WAFERS;
TECHNOLOGY;
TESTING;
TIN;
TITANIUM COMPOUNDS;
VEHICLES;
WAFER BONDING;
CHIP SCALE PACKAGES;
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EID: 63049092477
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/VPWJ.2008.4762237 Document Type: Conference Paper |
Times cited : (3)
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References (5)
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