New bit-parallel systolic multipliers for a class of GF(2m)

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 578-581

  Lee, Chiou Yng ^a   Lu, Erl Huei ^a   Lee, Jau Yien ^a  

^a CHANG GUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALL-ONE POLYNOMIAL; BIT PARALLEL SYSTOLIC MULTIPLIER; CYCLIC SHIFTING; EFFECTIVE ALGORITHMS; EQUALLY SPACED POLYNOMIALS; INNER PRODUCT; LOW LATENCY;

SYSTOLIC ARRAYS;

EID: 62949226214     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922303     Document Type: Conference Paper

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