A full adder based methodology for scaling operation in Residue Number System

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2002, Pages 891-894

  Soudris, D ^a   Dasygenis, M ^a   Mitroglou, K ^a   Tatas, K ^a   Thanailakis, A ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

C++ LANGUAGE; FULL ADDERS; HARDWARE COMPLEXITY; MATHEMATICAL DESCRIPTIONS; RESIDUE NUMBER SYSTEM; SOFTWARE TOOL; SYSTEMATIC METHODOLOGY; THROUGHPUT RATE; VHDL DESCRIPTION;

ADDERS; SOFTWARE DESIGN;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 62449091316     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046391     Document Type: Conference Paper

References (9)

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2. Soderstrand, M.A., W.K. Jenkins, G.A. Jullien, and F.J. Taylor, "Residue Number System: Modem Applications in Digital Signal Processing," IEEE Press, New York, 1986.
3. Jenkins, W.K., "Recent advances in residue number techniques for recursive digit filtering," IEEE Trans. Acoust, Signal Processing, vol.ASSP-27, no.1, pp. 19-30, Feb. 1979.
4. Garcia, A., A. Llioris, "A Look-Up Scheme for Scaling in the RNS," IEEE Trans. Computers, vol.48, no.7, pp. 748-751, Jul. 1999.
5. Jullien, G.A., "Residue Number Scaling and Other Operations Using ROM Arrays," IEEE Trans. Computers, vol.27, no.4, pp. 325-337, Apr. 1978.
6. Kameyama, M. and T. Higuchi, "A New Scaling Algorithm in Symmetric Residue Number System Based on Multiple-Valued Logic," IEEE Symp. Circuits and Systems, Tokyo, pp. 189-192, July. 1979.
7. Su, C.C. and H.Y. Lo, "An Algorithm for Scaling and Single Residue Error Correction in the Residue Number System," IEEE Trans. Computers, vol.39, no.8, pp. 1053-1064, Aug. 1990.
8. Soudris, D.J., M.M. Dasygenis, AT. Thanailakis, "A unified methodology for designing RNS & QRNS FA based converters," IEEE Int. Symp. On Circuits and Systems (ISCAS), Geneva, vol.I, pp. 20-23, May 2000.
9. Soudris, D.J., V. Paliouras, T. Stouraitis and C.E. Goutis, "A VLSI Design Methodology for RNS Full Adder Based Inner Product Architectures," IEEE Trans. Circuits and Systems-II," vol.44, no.4, pp. 315-318, April. 1997.