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Volumn , Issue , 2008, Pages 5029-5032

NEUSORT2.0: A multiple-channel neural signal processor with systolic array buffer and channel-interleaving processing schedule

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER FACTOR; RECORDING INSTRUMENTS;

EID: 61849155263     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (9)
  • 1
    • 85089791880 scopus 로고    scopus 로고
    • A 128-channel 6mw wireless neural recording ic with on-the-fly spike sorting and uwb transmitter
    • Feb
    • M. Chae et al., "A 128-channel 6mw wireless neural recording ic with on-the-fly spike sorting and uwb transmitter," in Proc. of ISSCC, Feb. 2008, vol. 7, pp. 146-147.
    • (2008) Proc. of ISSCC , vol.7 , pp. 146-147
    • Chae, M.1
  • 2
    • 85032751866 scopus 로고    scopus 로고
    • Signal processing challenges for neural prostheses
    • M. D. Linderman et al., "Signal processing challenges for neural prostheses," IEEE Signal Processing Magazine, vol. 25, no. 1, pp. 18-28, 2008.
    • (2008) IEEE Signal Processing Magazine , vol.25 , Issue.1 , pp. 18-28
    • Linderman, M.D.1
  • 3
    • 26444465132 scopus 로고    scopus 로고
    • Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems
    • Z. Zumsteg et al., "Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems," IEEE Trans. on Neural Systems and Rehabilitation Engineering, vol. 13, no. 3, pp. 272-279, 2005.
    • (2005) IEEE Trans. on Neural Systems and Rehabilitation Engineering , vol.13 , Issue.3 , pp. 272-279
    • Zumsteg, Z.1
  • 4
    • 29044441759 scopus 로고    scopus 로고
    • A three-dimensional neural recording microsystem with implantable data compression circuitry
    • R. H. Olsson et al., "A three-dimensional neural recording microsystem with implantable data compression circuitry," IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2796-2804, 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.12 , pp. 2796-2804
    • Olsson, R.H.1
  • 5
    • 33846258717 scopus 로고    scopus 로고
    • A low-power integrated circuit for a wireless 100-electrode neural recording system
    • R. R. Harrison et al., "A low-power integrated circuit for a wireless 100-electrode neural recording system," IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 123-133, 2007.
    • (2007) IEEE Journal of Solid-State Circuits , vol.42 , Issue.1 , pp. 123-133
    • Harrison, R.R.1
  • 6
    • 1542360848 scopus 로고    scopus 로고
    • Optimizing signal coding in neural interface system-on-a-chip modules
    • Sept
    • K. G. Oweiss et al., "Optimizing signal coding in neural interface system-on-a-chip modules," in Proc. of IEEE EMBS Conference, Sept. 2003, vol. 3, pp. 2216-2219.
    • (2003) Proc. of IEEE EMBS Conference , vol.3 , pp. 2216-2219
    • Oweiss, K.G.1
  • 7
    • 0034306387 scopus 로고    scopus 로고
    • Neural spike sorting under nearly 0-db signal-to-noise ratio using nonlinear energy operator and artificial neural-network classifier
    • K. H. Kim et al., "Neural spike sorting under nearly 0-db signal-to-noise ratio using nonlinear energy operator and artificial neural-network classifier," IEEE trans. on Biomedical Engineering, vol. 47, no. 10, pp. 1406-1411, 2000.
    • (2000) IEEE trans. on Biomedical Engineering , vol.47 , Issue.10 , pp. 1406-1411
    • Kim, K.H.1
  • 8
    • 61849148711 scopus 로고    scopus 로고
    • A neuron signature based spike feature extraction algorithm for on-chip implementation
    • Aug
    • Z. Yang et al., "A neuron signature based spike feature extraction algorithm for on-chip implementation," in Proc. of IEEE EMBS Conference, Aug. 2008.
    • (2008) Proc. of IEEE EMBS Conference
    • Yang, Z.1
  • 9


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.