Optimizing i-line lithography for 0.3-μm poly-gate manufacturing

Solid State Technology

Volumn 40, Issue 3, 1997, Pages

  Finders, Jo ^a   Tzviatkov, Plamen ^a   Ronse, Kurt ^a   Van Den Hove, Luc ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 6144231532     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (3)

1. P.Tzviatkov et al., "0.30-μm and Sub-0.30-μm i-Line Lithography for Random Logic Gates," Proceedings Interface, pp. 1-5, 1995.
2. K-Y. Kim, et al., "Implementation of i-Line Lithography with 0.30-μm Design Rules," Microlithography World, pp. 6-11, Autumn 1995.
3. R. Rogoff et al., "Photolithography Using the AERIAL Illuminator in a Variable-NA Wafer Stepper," Proceedings SPIE, Vol. 2726, pp. 54-71, 1996.