Advanced DRAMs drive high-AR etch advances

Semiconductor International

Volumn 32, Issue 2, 2009, Pages 18-22

  Welch, S ^a   Keswick, K ^a   Stout, P ^a   Kim, J ^a   Lee, W ^a   Doan, K ^a   Kim, H S ^a   Pu, B ^a  

^a Materials Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 61349100302     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (8)

1. International Technology Roadmap for Semiconductors, Front End Processes, 2004 Update, p. 33.
2. International Technology Roadmap for Semiconductors, Front End Processes, 2007 Edition, p. 31.
3. S.M. Ma, "Plasma Etch Enhanced Patterning Technology for Sub-45nm Logic and Memory Contacts," Applied Materials SPIE Technical Seminars, February 2007.
4. K. Kim and G. Jeong, "Memory Technologies for Sub-40-nm Node," IEDM Technical Digest Dec. 10. 2007, p. 27.
5. M. Vogt et al., "Introduction of PECVD Carbon Hardmasks (APFTM) for Sub-90-nm DRAM TechnolOgy." International Semiconductor Technology Conference, 2004.
6. M. Boufnichel et al., "Profile Control of High Aspect Ratio Trenches of Silicon. II. Study of the Mechanisms Responsible for Local Bowing Formation and Elimination of This Effect," Journal of Vacuum Science and Technology B, Vol. 21, No. 1, Jan. 28, 2003, p. 267.
7. R. Tran et al., "Extreme Edge Engineering - 2-mm Edge Exclusion Challenges and Cost-Effective Solutions for Yield Enhancement in High Volume Manufacturing for 200 and 300 mm Wafer Fabs," Advanced Semiconductor Manufacturing - IEEE Conference and Workshop, May 4, 2004, p, 453.
8. R. Gottscho et al., "Microscopic Uniformity in Plasma Etching," Journal of Vacuum Science Technology B, Vol. 10, No. 5, September 1992, p. 2133.