Study on LD-VHDL conversion for FPGA-based PLC implementation

International Journal of Advanced Manufacturing Technology

Volumn 40, Issue 11-12, 2009, Pages 1181-1190

  Du, Daoshan ^a   Liu, Yadong ^a   Guo, Xingui ^a   Yamazaki, Kazuo ^a   Fujishima, Makoto ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b DMG Mori Seiki Co   (Japan)

Author keywords

CSG; FPGA; Ladder diagram; PLC; VHDL

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER SOFTWARE; COMPUTERS; CONCURRENCY CONTROL; CONTOUR FOLLOWERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FIRMWARE; GRAPH THEORY; INTEGRATED CIRCUITS; LADDER NETWORKS; LADDERS; LINGUISTICS; MACHINE DESIGN; PROGRAMMABLE LOGIC CONTROLLERS;

CSG; FPGA; LADDER DIAGRAM; PLC; VHDL;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 60749121569     PISSN: 02683768     EISSN: 14333015     Source Type: Journal    
DOI: 10.1007/s00170-008-1426-4     Document Type: Article

References (16)

1. Auslander DM, Pawlowski C, Ridgely J (1998) Reconciling programmable logic controllers with mechatronics control software. Proceedings of the 1998 IEEE international conference on control applications, Trieste, Italy, pp 415-420
2. Ikeshita M, Takeda Y, Murakoshi H, Funakubo N, Miyazawa I (1999) Application of FPGA to high-speed programmable controller-development of the conversion program from SFC to Verilog. IEEE symposium on emerging technologies and factory automation, Piscataway, NJ, USA, vol 2, pp 1386-1390
3. Miyazawa I, Nagao T, Fukagawa M, Itoh Y, Mizuya T, Sekiguchi T (1999) Implementation of ladder diagram for programmable controller using FPGA. IEEE symposium on emerging technologies and factory automation, Piscataway, NJ, USA, vol 2, pp 1381-1385
4. Chen J, Patyra MJ (1994) VHDL modeling of a multivariable fuzzy logic controller hardware system. IEEE international conference on fuzzy systems. Piscataway, NJ, USA, vol 1, pp 129-132
5. Abdel-Hamid AT, Zaki M, Tahar S (2004) A tool converting finite state machine to VHDL. IEEE Canadian conference on electrical and computer engineering, Niagra Falls, Canada, vol 4, pp 1907-1910
6. K Kuusilinna V Lahtinen T Hamalainen J Saarinen 2001 Finite state machine encoding for VHDL synthesis IEE Comput Dig T 148 23 30
7. Adamski M, Monteiro JL (2000) From interpreted Petri net specification to reprogrammable logic controller design. IEEE international symposium on industrial electronics, Puebla, Mexico, vol 1, pp 13-19
8. Adamski M (1998) SFC, Petri nets and application specific logic controllers, Proceedings of the IEEE International Conference on Systems, Man and Cybernetics. IEEE, Piscataway, NJ, USA 1:728-733
9. M Uzam AH Jones 1998 Discrete event control system design using automation Petri nets and their ladder diagram implementation Int J Adv Manuf Technol 14 10 716 728
10. JS Lee PL Hsu 2005 An improved evaluation of ladder logic diagrams and Petri nets for the sequence controller design in manufacturing systems Int J Adv Manuf Technol 24 3-4 279 287
11. Welch JT (1992) Translating unrestricted relay ladder logic into Boolean form. Comput Ind 20-45
12. Shanta S, Dipali S (2005) A new generation of PLC-an FPGA based PLC. Proceedings of the SICE annual conference, Okayama, Japan, pp 2367-2370
13. Yadong L, Kazuo Y, Makoto F, Masahiko M (2005) Model-driven programmable logic controller design and FPGA-based hardware implementation. Proceedings of the ASME international design engineering technical conferences and computers and information in engineering conference, Long Beach, CA, USA, vol 4, pp 81-88
14. Asbenden PJ (2002) The designer's guide to VHDL. Morgan Kaufmann, San Diego
15. JI Lee SW Chun SJ Kang 2002 Virtual prototyping of PLC-based embedded system using object model of target and behavior model by converting RLL-to-state chart directly J Systems Archit 48 17 35
16. Falcione A, Krogh BH (1992) Design recovery for relay ladder logic. First IEEE conference on control applications, Dayton, OH, pp 90-98