NAND flash read/write cache directions for the personal computing platform

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 815-818

  Pon, Harry ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PLATFORMS; COMPUTING PLATFORMS; DATA ACCESS; MAGNETIC HARD DISK DRIVES; MEMORY INTERFACES; MEMORY SUBSYSTEMS; NAND FLASH MEMORIES; NAND FLASHES; NON VOLATILES; PCI EXPRESS; RANDOM ACCESS; USAGE MODELS; USER CONTROLS; USER EXPERIENCES;

COMPUTER ARCHITECTURE; HARD DISK STORAGE; INTEGRATED CIRCUITS; INTERFACES (COMPUTER); NAND CIRCUITS; PERSONAL COMPUTING;

FLASH MEMORY;

EID: 60749098540     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734667     Document Type: Conference Paper

References (4)

1. Pon, H, Rao, K, "A NAND Flash PC Platform Read Write Cache", NVSMW Proceedings, p 21-22. (2007).
2. Nobunaga, D, et.al, "A 50nm 8Gb NAND Flash Memory with l00MB/s Program Throughput and 200 MB/s DDR Interface", ISSCC Digest, p 426-427. (2008).
3. Pon, H, "Technology Scaling Impact on NOR and NAND Flash Memories and Their Applications", ICSICT 2006 Proceedings, p. 697-700
4. Grimsrud, K, Huffman, A, "New Advances in ONFI", 2007 Intel Developer Forum Presentation, www.onfi.org/docs/IDF-Spring-2007.pdf