Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 952-955

  Ma, Zhe ^a,b   Catthoor, Francky ^a,b   Vounckx, Johan ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CODE GENERATION; COMPLEX APPLICATIONS; EXECUTION TIME; HETEROGENEOUS MULTIPROCESSORS; MULTIPLE TASKS; OPTIMAL SOLUTIONS; PARALLEL PROCESSOR; SEQUENTIAL EXECUTION; SINGLE CHIPS; SOURCE CODES; SUBTASKS; SYSTEM-ON-A-CHIP;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING;

PARALLEL PROCESSING SYSTEMS;

EID: 60449095927     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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