Dry etch challenges in gate all around devices for sub 32 nm applications

ECS Transactions

Volumn 16, Issue 10, 2009, Pages 923-934

  Barnola, S ^a,d   Vizioz, C ^a   Vulliet, N ^a,b   Dupre C ^a,b   Ernst, T ^a   Gautier, P ^a   Arvet, C ^a,b   Guillaumot, B ^a,b   Bernard, E ^a,b   Pauliac Vaujeour, S ^a   Comboroure, C ^b   Hartmann, J M ^a   Borel, S ^a   Chevolleau, T ^c   Maffini Alvaro, V ^a   Becu S ^a  

^a CEA LETI   (France)

^b STMicroelelctronics   (France)

^c Joseph Fourier University   (France)

^d MINATEC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANISOTROPIC ETCHING; ASPECT RATIO; GERMANIUM COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

GATE-ALL-AROUND DEVICES; INDUCTIVE COUPLED PLASMA; ISOTROPIC ETCHING; REMOTE PLASMAS; SI/SIGE; SILICON ON INSULATOR WAFERS;

SI-GE ALLOYS;

EID: 59649124383     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2986854     Document Type: Conference Paper

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