Closed-loop modeling in future automation system engineering and validation

IEEE Transactions on Systems, Man and Cybernetics Part C: Applications and Reviews

Volumn 39, Issue 1, 2009, Pages 17-28

  Vyatkin, Valeriy ^a   Hanisch, Hans Michael ^b   Pang, Cheng ^a   Yang, Chia Han ^a  

^a UNIVERSITY OF AUCKLAND   (New Zealand)

^b MARTIN LUTHER UNIVERSITY HALLE WITTENBERG   (Germany)

Author keywords

Manufacturing automation; Mechatronics; Software reusability; Software verification and validation (V V)

Indexed keywords

AUTOMATION; COMPUTER SOFTWARE; COMPUTER SOFTWARE SELECTION AND EVALUATION; DESIGN; EMBEDDED SYSTEMS; ENTERPRISE RESOURCE PLANNING; FORMAL METHODS; FOURIER TRANSFORMS; INTELLIGENT MECHATRONICS; MECHATRONICS; MODEL STRUCTURES; REUSABILITY; SYSTEMS ENGINEERING; UNIFIED MODELING LANGUAGE; VERIFICATION;

AUTOMATION SOFTWARE; AUTOMATION SYSTEMS; CLOSED LOOPS; COMPONENT DESIGNS; ENGINEERING METHODOLOGY; FORMAL VERIFICATIONS; INDUSTRIAL AUTOMATION SYSTEMS; INFORMATION INFRASTRUCTURES; INTERNATIONAL ELECTROTECHNICAL COMMISSION (IEC) 61499; KEY FEATURE; MANUFACTURING AUTOMATION; MECHATRONIC COMPONENTS; SIMULINK (SOFTWARE); SOFTWARE REUSABILITY; SOFTWARE TOOLS; SYSTEM DEVELOPMENT; SYSTEM MODELLING; UNIFIED MODELING (UML); VALIDATION METHODOLOGIES; VALIDATION TECHNIQUES;

COMPUTER SOFTWARE REUSABILITY;

EID: 58649088691     PISSN: 10946977     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSMCC.2008.2005785     Document Type: Article

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