High-k etch performance for next-generation logic gate stacks

Solid State Technology

Volumn 51, Issue 12, 2008, Pages 18-22

  Wise, R ^a   Yan, W ^a   Zhang, Y ^a,c   Gani, N ^b   Sun, N ^b   Shen, M ^b   Lill, T ^b  

^a IBM MICROELECTRONICS   (United States)

^b APPLIED MATERIALS INC   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; GATE DIELECTRICS; GATES (TRANSISTOR); HYDROFLUORIC ACID; LOGIC GATES; NITRIDES; PLASMA ETCHING; SILICON COMPOUNDS; WET ETCHING;

BASED GATES; CAP LAYERS; GATE STACKS; HF SOLUTIONS; SUBSTRATE TEMPERATURES;

DRY ETCHING;

EID: 58249136945     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (9)

1. Tomimori et al., NEC, Japan patent application number 854306, 2004.
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3. G. P. Kota et al., "Dry Process International Symposium," p. 23, 2004.
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6. Mike Barnes et al., Inductively Coupled Plasma Source with Controllable Power Deposition, US Patent 6,507,155.
7. John Holland et. al, "An Advanced 300mm Etcher with Tunable Plasma Source for the Etching of <0.15mm Poly-Silicon Gates," 48th AVS Symposium, San Francisco, CA, 2001.
8. 3 Plasmas," J. Vac. Sci. Technol., A 24(1), 41, 2006.
9. J. S. Chickos, W. E. Acree, "Enthalpies of Sublimation of Organic and Organometallic Compounds," 1910-2001, J. of Phys. Chem. Ref. Data, Vol 31 No. 2, p537, 2002.