Augmenting a regular expression-based temporal logic with local variables

Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, FMCAD

Volumn , Issue , 2008, Pages

  Eisner, Cindy ^a   Fisman, Dana ^b  

^a IBM HAIFA RESEARCH LAB   (Israel)

^b HEBREW UNIVERSITY OF JERUSALEM   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

ASSERTION LANGUAGES; ATOMIC PROPOSITIONS; DISTRIBUTIVITY; FORMAL SEMANTICS; LOCAL VARIABLES; REGULAR EXPRESSIONS; SYSTEMVERILOG; TEMPORAL LOGIC FORMULAS;

ATOMIC PHYSICS; COMPUTER AIDED DESIGN; FORMAL LOGIC; INFORMATION THEORY; SEMANTICS; TEMPORAL LOGIC;

FORMAL METHODS;

EID: 58049144130     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FMCAD.2008.ECP.27     Document Type: Conference Paper

References (19)

1. D. Bustan, D. Fisman, and J. Havlicek. Automata construction for PSL. Technical Report MCS05-04, The Weizmann Institute of Science, May 2005.
2. D. Bustan and J. Havlicek. Some complexity results for SystemVerilog assertions. In Proc. CAV 2006, LNCS 4144, pages 205-218. Springer, 2006.
3. C. Eisner and D. Fisman. A Practical Introduction to PSL. Springer, 2006.
4. C. Eisner and D. Fisman. Proposed New Appendix B for IEEE 1850 (PSL). Technical Report H-0257, IBM, 2008.
5. C. Eisner, D. Fisman, and J. Havlicek. A topological characterization of weakness. In Proc. PODC '05, pages 1-8, New York, NY, USA, 2005. ACM Press.
6. C. Eisner, D. Fisman, J. Havlicek, Y. Lustig, A. McIsaac, and D. Van Campenhout. Reasoning with temporal logic on truncated paths. In Proc. CAV '03, LNCS 2725, pages 27-40. Springer-Verlag, July 2003.
7. C. Eisner, D. Fisman, J. Havlicek, A. McIsaac, and D. Van Campenhout. The definition of a temporal clock operator. In Proc. ICALP '03, LNCS 2719, pages 857-870. Springer-Verlag, June 2003.
8. M. J. Fischer and R. E. Lander. Propositional dynamic logic of regular programs. In J. Comput. Syst. Sci., pages 18(2), 194-211, 1979.
9. D. Fisman. On the characterization of until as a fixed point under clocked semantics. In Proc. Haifa Verification Conference, volume 4899 of LNCS, pages 19-33. Springer, 2007.
10. D. Harel, D. Kozen, and J. Tiuryn. Dynamic Logic. MIT Press, Cambridge, MA, USA, 2000.
11. J. Havlicek, N. Levi, H. Miller, and K. Shultz. Extended CBV statement semantics, partial proposal presented to the Accellera Formal Verification Technical Committee, April 2002. At http://www.eda.org/vfv/hm/att-0772/01- ecbv_statement_semantics.ps.gz.
12. J. Havlicek, K. Shultz, R. Armoni, S. Dudani, and E. Cerny. Notes on the semantics of local variables in Accellera SystemVerilog 3.1 concurrent assertions. Technical Report 2004.01, Accellera, May 2004.
13. IEEE Standard for Property Specification Language (PSL). IEEE Std 1850™-2005.
14. IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language. IEEE Std 1800™-2005.
15. M. Lange. Linear time logics around PSL: Complexity, expressiveness, and a little bit of succinctness. In Proc. CONCUR 2007.
16. M. T. Oliveira and A. J. Hu. High-level specification and automatic generation of IP interface monitors. In DAC '02: Proceedings of the 39th conference on Design automation, pages 129-134, New York, NY, USA, 2002. ACM.
17. A. Pnueli. A temporal logic of concurrent programs. Theoretical Computer Science, 13:45-60, 1981.
18. A. Seawright and F. Brewer. High-level symbolic construction technique for high performance sequential synthesis. In DAC '93: Proceedings of the 30th international conference on Design automation, pages 424-428, New York, NY, USA, 1993. ACM.
19. A. P. Sistla, M. Y. Vardi, and P. L. Wolper. The Complementation Problem for Büchi Automata, with Applications to Temporal Logic. Theoretical Computer Science, 49:217-237, 1987.