Supply-noise mitigation techniques in phase-locked loops

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 374-377

  Arakali, Abhijith ^a   Talebbeydokthi, Nema ^b   Gondi, Srikanth ^c   Hanumolu, Pavan Kumar ^a  

^a Oregon State University   (United States)

^b INTEL CORPORATION   (United States)

^c Kawasaki Microelectronics America Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKS; CMOS PROCESSES; IN PHASE; JITTER PERFORMANCES; NOISE MITIGATIONS; PLL ARCHITECTURES; POWER SUPPLIES; PRIOR ARTS; RING OSCILLATORS; SUPPLY NOISES;

ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER TRANSMISSION NETWORKS; ELECTRIC POWER UTILIZATION; JITTER; OSCILLATORS (ELECTRONIC); SPURIOUS SIGNAL NOISE;

PHASE LOCKED LOOPS;

EID: 58049088963     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681870     Document Type: Conference Paper

References (4)

1. V. von Kaenel et al., "A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation," IEEE J. Solid-State Circuits, vol. 31, pp. 1715 - 1722, Nov. 1996.
2. K. Chang et al., "A 0.44-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs," IEEE J. Solid-State Circuits,vol. 38, pp. 747 -754, May 2003.
3. S. Sidiropoulos et al., "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS Buffers," Symp. VLSI Circuits Dig., pp. 124 -127, June 2000.
4. G. Wei et al., "A 500-MHz MP/DLL clock generator for a 5-Gb/s backplane transceiver in 0.25 - μm CMOS," ISSCC Dig. Tech. Papers, pp. 464-465, Feb. 2003.