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Volumn , Issue , 2008, Pages 197-200

Pure logic CMOS based embedded non-volatile random access memory for low power RFID application

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; NETWORK ARCHITECTURE;

EID: 57849151645     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672057     Document Type: Conference Paper
Times cited : (11)

References (5)
  • 1
    • 84943130890 scopus 로고
    • A single poly EEPROM cell structure for use in standard CMOS processes
    • Ohsaki K., Asamoto N., Takagaki S., "A single poly EEPROM cell structure for use in standard CMOS processes," IEEE Journal of Solid-State Circuits, Vol. 29, Iss. 3, pp.311-316, 1994
    • (1994) IEEE Journal of Solid-State Circuits , vol.29 , Issue.ISS. 3 , pp. 311-316
    • Ohsaki, K.1    Asamoto, N.2    Takagaki, S.3
  • 2
    • 2442678914 scopus 로고    scopus 로고
    • Raszka J., Advani M., Tiwari V., Varisco L., Hacobian N.D., Mittal A., et al., Embedded flash memory for security applications in a 0.13μm CMOS logic process, Digest of Technical Papers of International Solid-State Circuit Conference, 1, pp.46-512, 2004
    • Raszka J., Advani M., Tiwari V., Varisco L., Hacobian N.D., Mittal A., et al., "Embedded flash memory for security applications in a 0.13μm CMOS logic process," Digest of Technical Papers of International Solid-State Circuit Conference, Vol. 1, pp.46-512, 2004
  • 3
    • 57849161745 scopus 로고    scopus 로고
    • http://www.impinj.com/ip/aeon-mtp.aspx?ekmensel=c580fa7b-22-0-1076-2
  • 4
    • 0016961262 scopus 로고
    • On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
    • Dickson J F., "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique," IEEE Journal of Solid-State Circuits, Vol.11, Iss. 3, pp. 374-378, 1976.
    • (1976) IEEE Journal of Solid-State Circuits , vol.11 , Issue.ISS. 3 , pp. 374-378
    • Dickson, J.F.1
  • 5
    • 43049152976 scopus 로고    scopus 로고
    • A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process
    • Park Jin-Young, Chung Yeonbae, "A low-voltage charge pump circuit with high pumping efficiency in standard CMOS logic process," Electron Devices and Solid-State Circuits, pp.317-320, 2007.
    • (2007) Electron Devices and Solid-State Circuits , pp. 317-320
    • Jin-Young, P.1    Chung, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.