Optimized nickel silicide process formation for high performance sub-65nm CMOS nodes

Proceedings - Electrochemical Society

Volumn 1, Issue , 2004, Pages 191-201

  Froment, B ^a   Carron, V ^b   Morand, Y ^d   Descombes, S ^d   Halimaoui, A ^a   Muller, M ^c   Pouydebasque, A ^c   Wacquant, F ^a   Ceccarelli, D ^a   DeJonghe, V ^c  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c NXP SEMICONDUCTORS   (Netherlands)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COBALT COMPOUNDS; DATABASE SYSTEMS; DIFFUSION IN SOLIDS; ELECTRIC CONDUCTIVITY; NICKEL COMPOUNDS; OPTIMIZATION; PHYSICAL VAPOR DEPOSITION; THERMAL EFFECTS;

ELECTRICAL QUALITY; NICKEL DEPOSITION; NICKEL SILICIDE; TEMPERATURE ANNEALING;

CMOS INTEGRATED CIRCUITS;

EID: 5744248253     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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