Drain breakdown voltage in MuGFETs: Influence of physical parameters

IEEE Transactions on Electron Devices

Volumn 55, Issue 12, 2008, Pages 3503-3506

  Lee, Chi Woo ^a   Afzalian, Aryan ^a   Yan, Ran ^a   Akhavan, Nima Dehdashti ^a   Xiong, Weize ^b   Colinge, Jean Pierre ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Breakdown voltage; Floating body effects; Impact ionization; Multiple gate MOSFET (MuGFET); Silicon on insulator (SOI)

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC CONDUCTIVITY; FINS (HEAT EXCHANGE); IMPACT IONIZATION; IONIZATION OF GASES; SEMICONDUCTING SILICON COMPOUNDS; SILICON;

ACTIVE AREAS; AND GATES; BREAK DOWN VOLTAGES; BREAKDOWN VOLTAGE; CHANNEL DOPING; DOPING CONCENTRATIONS; ELECTROSTATIC CONTROLS; FIN WIDTHS; FLOATING-BODY EFFECTS; MULTIGATE MOSFETS; MULTIPLE-GATE MOSFET (MUGFET); PHYSICAL PARAMETERS; SILICON-ON-INSULATOR (SOI);

MOSFET DEVICES;

EID: 57149148263     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2006546     Document Type: Article

References (10)

1. J. P. Colinge, "Multi-gate SOI MOSFETs," Solid State Electron., vol. 48, no. 9/10, pp. 897-905, Sep./Oct. 2004.
2. S. Okhonin, M. Nagoga, E. Carman, R. Beffa, and E. Faraoni, "New generation of Z-RAM, in IEDM Tech. Dig., 2007, pp. 925-928.
3. [Online]. Available: http://www.silvaco.com
4. H. S. Wong, H. White, J. Krutsck, and R. V. Booth, "Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFETs," Solid State Electron., vol. 30, no. 9, pp. 953-968, Sep. 1987.
5. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, "Modeling of ultrathin double-gate nMOS/SOI transistors," IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 715-720, May 1994.
6. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, p. 347.
7. C.-W. Lee, S.-R.-N. Yun, C.-G. Yu, J.-T. Park, and J. P. Colinge, "Device design guidelines for nano-scale MuGFETs," Solid State Electron., vol. 51, no. 3, pp. 505-510, Mar. 2007.
8. J. G. Fossum, J.-Y. Choi, and R. Sundaresan, "SOI design for competitive CMOS VLSI," IEEE Trans. Electron Device, vol. 37, no. 3, pp. 724-729, Mar. 1990.
9. N. Kistler, E. Ver Ploeg, J. Woo, and J. Plummer, "Dependence of fully depleted SOI MOSFET breakdown voltage on film thickness and channel length, in Proc. IEEE Int. SOI Conf., 1992, pp. 128-129.
10. J. P. Colinge, FinFETs and Other Multi-Gate Transistors. New York: Springer-Verlag, 2007, p. 18.